The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a capacitor with a multilayer dielectric layer.
As a semiconductor memory device becomes highly integrated, an area for a capacitor is reduced, making it difficult to obtain a high capacitance from the capacitor. Therefore, there has been proposed a number of methods to ensure the high capacitance of the capacitor within a limited area. One method is to form a dielectric layer of a high-k dielectric material.
Instead of oxide nitride oxide (ONO) or aluminium oxide (Al2O3), zirconium (ZrO2) having a higher dielectric constant has been widely used in recent years.
However, when this high-k dielectric material alone is used for the dielectric layer, leakage current characteristics of a capacitor may be degraded.
To overcome this limitation, researching efforts have been made to fabricate a capacitor including a multilayer dielectric layer with an aluminum oxide layer interposed within high-k dielectric material.
The typical method for fabricating the capacitor will be described in more detail with reference to FIGS. 1A to 1E.
FIGS. 1A to 1E illustrate a typical method for fabricating a capacitor. More specifically, a cylinder-type capacitor having excellent capacitance characteristic is illustrated.
Referring to FIG. 1A, an interlayer dielectric layer 11 with a conductive plug 12 is formed over a substrate (not shown) with a given lower structure.
A nitride layer 13 and a mold oxide layer 14 are sequentially formed over the interlayer dielectric layer 11. The nitride layer 13 serves as an etch stop layer, and the mold oxide layer 14 defines a region where a lower electrode will be formed. The mold oxide layer 14 may include a stacked structure of a phosphorus silicate glass (PSG) or boron phosphorus silicate glass (BPSG) layer 14A and a plasma enhanced tetraethyl orthosilicate (PETEOS) layer 14B.
Referring to FIG. 1B, the mold oxide layer 14 and the nitride layer 13 are etched to expose a given portion of the conductive plug 12, thereby forming a lower electrode region 15.
Referring to FIG. 1C, a TiN layer 16 for a lower electrode is formed over the lower electrode region 15 and the mold oxide layer 14.
Referring to FIG. 1D, a chemical mechanical polishing (CMP) process is performed until the top surface of the mold oxide layer 14 is exposed. The mold oxide layer 14 is removed by a wet etching process, thereby forming a cylinder type lower electrode 16A with separation from neighboring electrodes.
Referring to FIG. 1E, a first dielectric layer 17 is formed over the lower electrode 16A and the nitride layer 13. The first dielectric layer 17 may be formed of a high-k dielectric material, e.g., zirconium oxide.
Although not shown, a second dielectric layer is formed of aluminum oxide over the first dielectric layer 17, and a third dielectric layer is formed of zirconium oxide over the second dielectric layer. An upper electrode is formed over the third dielectric layer. In this way, the capacitor is fabricated.
As described above, the aluminum oxide layer for enhancing the leakage current characteristic is formed within the high-k material for ensuring the static capacitance, thereby improving the capacitance and leakage current characteristics simultaneously.
Particularly, the high-k dielectric material is formed at a low temperature, thereby improving step coverage characteristics. Crystallization of the formed high-k dielectric material is increased by depositing the aluminum oxide layer at a high temperature, thereby increasing the static capacitance of the capacitor. However, the method for fabricating the capacitor using the typical process of forming the dielectric layer has the following limitations.
First, referring to FIG. 2, when a cylinder-type capacitor is fabricated using the typical process of forming the dielectric layer, the cylinder-type lower electrodes can be touching while the zirconium oxide layer of the first dielectric layer is excessively crystallized during the process of depositing the aluminum oxide layer at a high temperature. This causes a dual bit fail in a reliability test.
Second, when an another capacitor, such as a concave-type capacitor is fabricated by using the typical process of forming the dielectric layer, a dual bit fail does not occur, but the total static capacitance of the capacitor is reduced. This is because the aluminum oxide layer used for ensuring the leakage current characteristic of the capacitor has a dielectric constant smaller than that of the zirconium oxide layer.
Therefore, there is a need for technologies that can ensure the leakage current characteristic of the capacitor, increase the static capacitance of the capacitor, and prevent the lower electrodes of the cylinder-type capacitor from touching.